The present invention relates to an improved semiconductor construction of the twin well (often called "twin tub") type.
The twin well type of semiconductor construction is discussed in "Twin-Tub CMOS - A Technology for VLSI Circuits", Parrillo et al., Paper 29.1, IEEE Conference, 1980. In this type of semiconductor construction, the initial step is the formation of p and n type wells in the underlying substrate, typically a high-resistance semiconductor. One well is formed by conventional masking, and the first well area is oxidized to provide the mask for forming the complementary well, resulting in the wells being self-aligned. Complementary n.sup.+ and p.sup.+ areas are thereafter formed in the wells, as discussed in the referenced paper.
While the twin well technique of semiconductor construction has many advantages, it has been found that there is significant compensation between the wells at their borders as the chip operates. When the wells are oxidized the p impurity at the substrate surface (typically boron) is depleted and the n impurity (phosphorous or arsenic) builds up. Because of this compensation, the border location between the wells at the substrate migrates into the original n well region. To allow for such border migration, there must be significant spacing between the adjacent n.sup.+ and p.sup.+ areas formed in the wells, limiting the number of usable areas which can be formed in a substrate of given dimensions.